74LVX132 Low Voltage Quad 2-Input NAND Schmitt Trigger
October 1996
Revised February 2005
74LVX132
Low Voltage Quad 2-Input NAND Schmitt Trigger
General Description
The LVX132 contains four 2-input NAND Schmitt Trigger
Gates. The pin configuration and function are the same as
the LVX00 but the inputs have hysteresis between the pos-
itive-going and negative-going input thresholds, which are
capable of transforming slowly changing input signals into
greater noise margins than conventional gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX132M
74LVX132SJ
74LVX132MTC
74LVX132MTCX_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
Y
n
漏 2005 Fairchild Semiconductor Corporation
DS012159
Descriptions
Inputs
Outputs
www.fairchildsemi.com