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74LVX125MTCX_NL Datasheet

  • 74LVX125MTCX_NL

  • Low Voltage Quad Buffer with 3-STATE Outputs

  • 6頁

  • FAIRCHILD

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74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs
February 1994
Revised February 2005
74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVX125 contains four independent non-inverting buff-
ers with 3-STATE outputs. The inputs tolerate voltages up
to 7V allowing the interface of 5V systems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX125M
74LVX125SJ
74LVX125MTC
74LVX125MTCX_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Pin Descriptions
OE
n
Pin Names
A
n
OE
n
O
n
Description
Inputs
Output Enable Inputs
Outputs
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
Z High Impedance
X Immaterial
Inputs
A
n
L
H
X
Output
O
n
L
H
Z
漏 2005 Fairchild Semiconductor Corporation
DS012007
www.fairchildsemi.com

74LVX125MTCX_NL 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 4

  • 4

  • Non-Inverting

  • 3.6 V

  • 2 V

  • + 85 C

  • SMD/SMT

  • TSSOP-14

  • Reel

  • - 4 mA

  • LVX

  • CMOS

  • 4 mA

  • - 40 C

  • 4

  • 3-State

  • 13.6 ns at 2.7 V, 9.7 ns at 3.3 V

  • 2500

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