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74LVX112SJ Datasheet

  • 74LVX112SJ

  • Low Voltage Dual J-K Flip-Flops with Preset and Clear

  • 7頁

  • FAIRCHILD

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74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear
October 1996
Revised December 2003
74LVX112
Low Voltage Dual J-K Flip-Flops with Preset and Clear
General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has
independent inputs (J, K, PRESET, CLEAR, and CLOCK)
and outputs (Q, Q). These devices are edge sensitive and
change states synchronously on the negative going transi-
tion of the clock pulse. Triggering occurs at a voltage level
of the clock and is not directly related to the transition time.
Clear and Preset are independent of the clock and are
accomplished by a low logic level on the corresponding
input. The J and K inputs can change when the clock is in
either state without affecting the flip-flop, provided that they
are in the desired state during the recommended setup and
hold times relative to the falling edge of the clock.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s
Input voltage level translation from 5V鈥?V
s
Ideal for low power/low noise 3.3V applications
Ordering Code:
Order Number
74LVX112M
74LVX112SJ
74LVX112MTC
Package Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
J
1
, J
2
, K
1
, K
2
CLK
1
, CLK
2
CLR
1
, CLR
2
PR
1
, PR
2
Q
1
, Q
2
, Q
1
, Q
2
Data Inputs
Clock Pulse Inputs (Active Falling edge)
Direct Clear Inputs (Active LOW)
Direct Preset Inputs (Active LOW)
Description
漏 2003 Fairchild Semiconductor Corporation
DS012158
www.fairchildsemi.com

74LVX112SJ 產(chǎn)品屬性

  • 47

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74LVX

  • 設(shè)置（預(yù)設(shè)）和復(fù)位

  • JK 型

  • 差分

  • 2

  • 1

  • 150MHz

  • 8.5ns

  • 負(fù)邊沿

  • 4mA，4mA

  • 2 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.209"，5.30mm 寬）

  • 管件

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