74LVX02 Low Voltage Quad 2-Input NOR Gate
May 1993
Revised February 2005
74LVX02
Low Voltage Quad 2-Input NOR Gate
General Description
The LVX02 contains four 2-input NOR gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code
Order Number
74LVX02M
74LVX02SJ
74LVX02MTC
74LVX02MTCX_NL
(Note 1)
Package
Number
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
漏 2005 Fairchild Semiconductor Corporation
DS011600
www.fairchildsemi.com