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74LVTH162373MTX Datasheet

  • 74LVTH162373MTX

  • Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs an...

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74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25鈩?Series Resistors in the
Outputs
October 2000
Revised November 2000
74LVTH162373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs and
25
鈩?/div>
Series Resistors in the Outputs
General Description
The LVTH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LVTH162373 is designed with equivalent 25
鈩?/div>
series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH162373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162373 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs include equivalent series resistance of 25
鈩?/div>
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Functionally compatible with the 74 series 16373
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Order Number
74LVTH162373MEA
74LVTH162373MEX
(Note 1)
74LVTH162373MTD
74LVTH162373MTX
(Note 1)
Package
Number
MS48A
MS48A
MTD48
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TUBES]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1:
Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
漏 2000 Fairchild Semiconductor Corporation
DS500354
www.fairchildsemi.com

74LVTH162373MTX 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 74LVTH

  • D 型透明鎖存器

  • 8:8

  • 三態(tài)

  • 2.7 V ~ 3.6 V

  • 2

  • 1.4ns

  • 12mA，12mA

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 48-TSSOP

  • 帶卷 (TR)

74LVTH162373MTX相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
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  • 英文版
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    Quad 2-input NAND gate
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    Quad 2-input NOR gate
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    Quad 2-input NAND gate
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    Hex inverter
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    Quad 2-input AND gate
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    Triple 3-input NAND gate
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    Triple 3-input AND gate
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    Hex inverting Schmitt-trigger
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    Dual 4-input NAND gate
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    Triple 3-input NOR gate
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    Quad 2-input OR gate
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    Dual D-type flip-flop with set and reset; positive-edge trig...
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    Dual D-type flip-flop with set and reset; positive-edge trig...
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    Quad 2-input EXCLUSIVE-OR gate
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    QUADRUPLE 2 INPUT POSITIVE NAND GATES
    TI [Texas ...
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    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...
  • 英文版
    Quad 2-input NAND gate
    PHILIPS
  • 英文版
    Quad 2-input NAND gate
    PHILIPS [N...

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