intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
鈩?/div>
series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
A Port outputs include equivalent series resistance of
25
鈩?/div>
making external termination resistors unnecessary
and reducing overshoot and undershoot
s
A Port outputs source/sink
鹵
12 mA.
B Port outputs source/sink
鈭?/div>
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 162245
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
s
Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
74LVT162245G
(Note 1)(Note 2)
74LVT162245MEA
(Note 2)
74LVT162245MTD
(Note 2)
74LVTH162245G
(Note 1)(Note 2)
74LVTH162245MEA
74LVTH162245MEX
74LVTH162245MTD
74LVTH162245MTX
Package Number
BGA54A
(Preliminary)
MS48A
MTD48
BGA54A
MS48A
MS48A
MTD48
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1:
Ordering code 鈥淕鈥?indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2002 Fairchild Semiconductor Corporation
DS012446
www.fairchildsemi.com
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