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74LVQ74T Datasheet

  • 74LVQ74T

  • DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

  • 81.62KB

  • 11頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LVQ74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 250 MHz (TYP.) at V
CC
= 3.3V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.2 V (TYP.) at V
CC
= 3.3V
75鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ74M
74LVQ74T
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/10

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