74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
June 1993
Revised June 2001
74LVQ240
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
Features
s
Ideal for low power/low noise 3.3V applications
s
Implements patented EMI reduction circuitry
s
Available in SOIC JEDEC, SOIC EIAJ, and QSOP pack-
ages
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Improved latch-up immunity
s
Guaranteed incident wave switching into 75
鈩?/div>
s
4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ240SC
74LVQ240SJ
74LVQ240QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
Inputs
OE
1
I
n
L
H
X
Inputs
OE
2
L
L
H
H
=
HIGH Voltage Level
X
=
Immaterial
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
I
n
L
H
X
L
=
LOW Voltage Level
Z
=
High Impedance
Connection Diagram
L
L
H
(Pins 3, 5, 7, 9)
H
L
Z
漏 2001 Fairchild Semiconductor Corporation
DS011611
www.fairchildsemi.com
next