74LVQ174 Datasheet

IC型號(hào)：
74LVQ174
PDF描述：
Low Voltage Hex D-Type Flip-Flop with Master Reset
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85.33KB
PDF頁數(shù)：
6頁
芯片廠家：
FAIRCHILD

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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset

May 1998

74LVQ174

Low Voltage Hex D-Type Flip-Flop with Master Reset

General Description

The LVQ174 is a high-speed hex D-type flip-flop. The device

is used primarily as a 6-bit edge-triggered storage register.

The information on the D inputs is transferred to storage dur-

ing the LOW-to-HIGH clock transition. The device has a

Master Reset to simultaneously clear all flip-flops.

Features

Ideal for low power/low noise 3.3V applications

Guaranteed simultaneous switching noise level and

dynamic threshold performance

Guaranteed pin-to-pin skew AC performance

Guaranteed incident wave switching into 75鈩?/div>

Ordering Code:

Order Number

74LVQ174SC

74LVQ174SJ

Package Number

M16A

M16D

Package Description

16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC

16-Lead Molded Small Outline Package, SOIC EIAJ

Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.

Logic Symbols

Connection Diagram

Pin Assignment for

SOIC JEDEC and EIAJ

DS011353-1

IEEE/IEC

DS011353-3

Pin Descriptions

Pin Names

鈥揇

鈥換

DS011353-2

Description

Data Inputs

Clock Pulse Input

Master Reset Input

Outputs

漏 1998 Fairchild Semiconductor Corporation

DS011353

www.fairchildsemi.com

型號(hào)

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