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74LVQ138M Datasheet

  • 74LVQ138M

  • 3 TO 8 LINE DECODER INVERTING

  • 9頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
74LVQ138
3 TO 8 LINE DECODER (INVERTING)
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.5 ns (TYP.) at V
CC
= 3.3V
COMPATIBLE WITH TTL OUTPUT
LOW POWER DISSIPATION:
I
CC
= 4
碌
A (MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.2 V (TYP.) at V
CC
= 3.3V
75
鈩?/div>
TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ138M
74LVQ138T
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go high.
Three enable inputs are provided to ease
cascade connection and application of address
decoders for memory systems.
It has better speed performance at 3.3V than 5V
LSTTL family combinad with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVQ138 is a low voltage CMOS 3 TO 8 LINE
DECODER
(INVERTING)
fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
It is ideal for low power and low noise 3.3V
applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/9

74LVQ138M 產(chǎn)品屬性

  • STMicroelectronics

  • 編碼器、解碼器、復(fù)用器和解復(fù)用器

  • Decoder / Demultiplexer

  • 74L

  • 3 / 8

  • 3.6 V

  • 2 V

  • + 85 C

  • SMD/SMT

  • SOP-16

  • Tube

  • - 40 C

  • 3

  • 8

  • 50

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