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74LVC3G04DP Datasheet

  • 74LVC3G04DP

  • Triple inverter

  • 13頁

  • PHILIPS

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74LVC3G04
Triple inverter
Rev. 01 鈥?4 May 2004
Product data sheet
1. General description
The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully speci鏗乪d for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging back鏗俹w current through the device when it
is powered down.
The 74LVC3G04 provides three inverting buffers.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
鹵24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
SOT505-2 and SOT765-1 package
Speci鏗乪d from
鈭?0 擄C
to +85
擄C
and
鈭?0 擄C
to +125
擄C.
s
s
s
s
s
s
s

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