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74LVC245AMTR Datasheet

  • 74LVC245AMTR

  • LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (NOT INVERTED) HIGH P...

  • 9頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LVC245A
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER
(NOT INVERTED) HIGH PERFORMANCE
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS
HIGH SPEED: t
PD
= 6.3ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVC245AM
T&R
74LVC245AMTR
74LVC245ATTR
DESCRIPTION
The 74LVC245A is a low voltage CMOS OCTAL
BUS TRANSCEIVER (3-STATE) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for 1.65 to 3.6
V
CC
operations and low power and low noise
applications.
This IC is intended for two-way asynchronous
communication between data buses and the
PIN CONNECTION AND IEC LOGIC SYMBOLS
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
February 2002
.
1/9

74LVC245AMTR 產(chǎn)品屬性

  • 74LVC245A View All Specifications

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74LVC

  • 收發(fā)器，非反相

  • 1

  • 8

  • 24mA，24mA

  • 1.65 V ~ 3.6 V

  • -55°C ~ 125°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 20-SO

  • 帶卷 (TR)

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