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74LS73A Datasheet

  • 74LS73A

  • Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops wit...

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DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
August 1986
Revised March 2000
DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.
Ordering Code:
Order Number
DM74LS73AM
DM74LS73AN
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Inputs
CLR
L
H
H
H
H
H
CLK
X
鈫?/div>
鈫?/div>
鈫?/div>
鈫?/div>
H
J
X
L
H
L
H
X
K
X
L
L
H
H
X
Q
0
Q
L
Q
0
H
L
Toggle
Q
0
Outputs
Q
H
Q
0
L
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
鈫?=
Negative going edge of pulse.
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
漏 2000 Fairchild Semiconductor Corporation
DS006372
www.fairchildsemi.com

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