DM74LS257B 3-STATE Quad 2-Data Selectors/Multiplexers
June 1989
Revised November 1999
DM74LS257B
3-STATE Quad 2-Data Selectors/Multiplexers
General Description
These Schottky-clamped high-performance multiplexers
feature 3-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a HIGH or LOW logic level. To minimize the pos-
sibility that two outputs will attempt to take a common bus
to opposite logic levels, the output enable circuitry is
designed such that the output disable times are shorter
than the output enable times.
This 3-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL reg-
isters for data retention throughout the system.
Features
s
3-STATE versions LS157 and LS158 with same pinouts
s
Schottky-clamped for significant improvement in A-C
performance
s
Provides bus interface from multiple sources in
high-performance systems
s
Average propagation delay from data input 12 ns
s
Typical power dissipation: 50 mW
Ordering Code:
Order Number
DM74LS257BM
DM74LS257BN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Logic Diagram
Function Table
Inputs
Output
Control
H
L
L
L
L
H
=
HIGH Level
L
=
LOW Level
Output Y
A
X
L
H
X
X
B
X
X
X
L
H
LS257
Z
L
H
L
H
Select
X
L
L
H
H
X
=
Don鈥檛 Care
Z
=
High Impedance (off)
漏 1999 Fairchild Semiconductor Corporation
DS006417
www.fairchildsemi.com
1
2
3
4
5
