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74LS09 Datasheet

  • 74LS09

  • Quad 2-Input AND Gates with Open-Collector Outputs

  • 51.22KB

  • 4頁

  • FAIRCHILD

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DM74LS09 Quad 2-Input AND Gates with Open-Collector Outputs
August 1986
Revised March 2000
DM74LS09
Quad 2-Input AND Gates with Open-Collector Outputs
General Description
This device contains four independent gates each of which
performs the logic AND function. The open-collector out-
puts require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Where:
N
1
(I
OH
)
=
total maximum output high current
for all outputs tied to pull-up resistor
N
2
(I
IH
)
=
total maximum input high current for
all inputs tied to pull-up resistor
N
3
(I
IL
)
=
total maximum input low current for
all inputs tied to pull-up resistor
Ordering Code:
Order Number
DM74LS09M
DM74LS09N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel.
Connection Diagram
Function Table
Y
=
AB
Inputs
A
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
B
L
H
L
H
Y
L
L
L
H
漏 2000 Fairchild Semiconductor Corporation
DS006348
www.fairchildsemi.com

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