Preliminary
74LCXZ164245 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs (Preliminary)
May 2001
Revised May 2001
74LCXZ164245
16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs (Preliminary)
General Description
The 74LCXZ164245 is a dual supply, 16-bit, translating
transceiver that is designed for two-way asynchronous
communication between busses at different supply volt-
ages. This device is suited for PCMCIA and other real-time
configurable I/O applications that utilize mixed power sup-
plies.
The 74LCXZ164245 is designed to Power-Up and Power-
Down into a High Impedance state (outputs disabled). The
feature eliminates the need to power-up in a specific
sequence to avoid drawing excessive current.
The A Port interfaces with the lower voltage bus (2.3V to
3.6V), and the B Port interfaces with the higher voltage bus
(3.0V to 5.5V). This dual supply design allows for transla-
tion from low voltage busses (2.3V to 3.6V) to busses at a
higher potential, up to 5.5V. The 74LCXZ164245 is
intended to be used in applications where the A Port is con-
nected to the 3.0V host system, and the B Port is con-
nected to the PCMCIA card slots.
Furthermore, when both OE鈥檚 are HIGH, the B Port I/O pins
are disabled, and both B Port I/O connections and B Port
V
CC
are allowed to float. This feature permits PCMCIA
cards to be inserted and removed during normal operation.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports; Receive (active-LOW) enables data from
B Ports to A Ports. The Output Enable (OE
1
, OE
2
) inputs,
when HIGH, disable their associated ports by placing the
I/Os in HIGH-Z condition. The 74LCXZ164245 is designed
so that the control pins (T/R
n
, OE
n
) are powered by V
CCA
,
so that V
CCB
may be removed when the I/Os are disabled.
The 74LCXZ164245 is suitable for mixed voltage applica-
tions such as notebook computers using a 3.3V CPU and
5.0V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
s
Bidirectional interface between 3V busses and
5V busses
s
Supports live insertion and withdrawal (Note 1)
s
Outputs source/sink up to 24 mA
s
Uses patented Quiet Series
錚?/div>
noise/EMI reduction
circuitry
s
Functionally compatible with the 74 series 16245
s
Port B I/O may be disabled by use of OE
n
or removal of
B Port V
CC
s
Port B V
CC
may be removed when OE
n
is used to
disable I/O鈥檚
s
Port B V
CC
removal may occur coincident with rising
edge of OE
n
s
Configurable as one 16-bit or two 8-bit transceivers
s
Unrestricted power-up sequencing
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor; the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCXZ164245MTD
Package
Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Quiet Series錚?is a trademark of Fairchild Semiconductor Corporation.
漏 2001 Fairchild Semiconductor Corporation
DS500385
www.fairchildsemi.com
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