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74LCX162373MTD Datasheet

  • 74LCX162373MTD

  • Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs...

  • 10頁(yè)

  • FAIRCHILD

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74LCX162373 Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26鈩?Series
Resistor
February 2001
Revised August 2001
74LCX162373
Low Voltage 16-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
and 26
鈩?/div>
Series Resistor
General Description
The LCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX162373 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with capability of interfacing to a 5V signal
environment. The 26
鈩?/div>
series resistor in the output helps
reduce output overshoot and undershoot.
The LCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
I
5V tolerant inputs and outputs
I
2.3V鈥?.6V V
CC
specifications provided
I
Equivalent 26
鈩?/div>
series resistor outputs
I
6.2 ns t
PD
max (V
CC
=
3.3V), 20
碌
A I
CC
max
I
Power down high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
鹵
12 mA output drive (V
CC
=
3.0V)
I
Implements patented noise/EMI reduction circuitry
I
Latch-up performance exceeds 500 mA
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
I
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1:
To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCX162373GX
(Note 2)
74LCX162373MEA
(Note 3)
74LCX162373MTD
(Note 3)
Package Number
BGA54A
(Preliminary)
MS48A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
漏 2001 Fairchild Semiconductor Corporation
DS500443
www.fairchildsemi.com

74LCX162373MTD 產(chǎn)品屬性

  • 38

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 74LCX

  • D 型透明鎖存器

  • 8:8

  • 三態(tài)

  • 2 V ~ 3.6 V

  • 2

  • 1.5ns

  • 12mA，12mA

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 48-TSSOP

  • 管件

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