3.0V.
ing CMOS low power dissipation.
鈩?/div>
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
5.3 ns t
PD
max (V
CC
=
3.0V), 20
碌
A I
CC
max
s
Power down high impedance inputs and outputs
s
鹵
12 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
74LCX162244GX
(Note 1)
74LCX162244MEA
(Note 2)
74LCX162244MTD
(Note 2)
Package Number
BGA54A
(Preliminary)
MS48A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
BGA package available in Tape and Reel only.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
漏 2001 Fairchild Semiconductor Corporation
DS500471
www.fairchildsemi.com