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74LCX125TTR Datasheet

  • 74LCX125TTR

  • LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE) WITH 5V TOLERANT ...

  • 217.21KB

  • 12頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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74LCX125
LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
PD
= 5.2 ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX125MTR
74LCX125TTR
DESCRIPTION
The 74LCX125 is a low voltage CMOS QUAD
BUS BUFFER fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 5
1/12

74LCX125TTR 產(chǎn)品屬性

  • 74LCX125 View All Specifications

  • 1

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74LCX

  • 緩沖器/線路驅(qū)動(dòng)器，非反相

  • 4

  • 1

  • 24mA，24mA

  • 2 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 14-TSSOP（0.173"，4.40mm 寬）

  • 14-TSSOP

  • Digi-Reel®

  • 497-6649-6

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