74LCX06 Low Voltage Hex Inverter/Buffer with Open Drain Outputs
October 1999
Revised February 2005
74LCX06
Low Voltage Hex Inverter/Buffer with Open Drain Outputs
General Description
The LCX06 contains six inverters/buffers. The inputs toler-
ate voltages up to 7V allowing the interface of 5V systems
to 3V systems.
The outputs of the LCX06 are open drain and can be con-
nected to other open drain outputs to implement active
LOW wire AND or active HIGH wire OR functions.
The 74LCX06 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs
s
2.3V鈥?.6V V
CC
specifications provided
s
3.7 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
3.0V)
s
Power down high impedance inputs and outputs
s
24 mA output drive (V
CC
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
Functionally compatible with 74 series 05
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Ordering Code:
Order Number
74LCX06M
74LCX06MX_NL
(Note 1)
74LCX06SJ
74LCX06MTC
74LCX06MTCX_NL
(Note 1)
Package
Number
M14A
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
n
O
n
Description
Inputs
Outputs
漏 2005 Fairchild Semiconductor Corporation
DS500237
www.fairchildsemi.com
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