74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
March 1995
Revised January 2005
74LCX00
Low Voltage Quad 2-Input NAND Gate
with 5V Tolerant Inputs
General Description
The LCX00 contains four 2-input NAND gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
The 74LCX00 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs
s
2.3V鈥?.6V V
CC
specifications provided
s
5.2 ns t
PD
max (V
CC
=
3.3V), 10
碌
A I
CC
max
s
Power down high impedance inputs and outputs
s
鹵
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds JEDEC 78 conditions
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Leadless Pb-Free DQFN package
Ordering Code:
Order Number
74LCX00M
74LCX00MX_NL
(Note 2)
74LCX00SJ
74LCX00BQX
(Note 1)
74LCX00MTC
74LCX00MTCX_NL
(Note 2)
Package
Number
M14A
M14A
M14D
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
MTC14
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
DQFN package available in Tape and Reel only.
Note 2:
鈥淿NL鈥?package available in Tape and Reel only.
漏 2005 Fairchild Semiconductor Corporation
DS012408
www.fairchildsemi.com