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74HCT73 Datasheet

  • 74HCT73

  • Dual JK flip-flop with reset; negative-edge trigger

  • 21頁(yè)

  • PHILIPS

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74HC73
Dual JK 鏗俰p-鏗俹p with reset; negative-edge trigger
Rev. 03 鈥?12 November 2004
Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is speci鏗乪d in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK 鏗俰p-鏗俹p featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
s
Low-power dissipation
s
Complies with JEDEC standard no. 7A
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Speci鏗乪d from
鈭?0 擄C
to +80
擄C
and from
鈭?0 擄C
to +125
擄C.

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