54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register
December 1994
54F 74F676
16-Bit Serial Parallel-In Serial-Out Shift Register
General Description
The 鈥橣676 contains 16 flip-flops with provision for synchro-
nous parallel or serial entry and serial output When the
Mode (M) input is HIGH information present on the parallel
data (P
0
鈥揚(yáng)
15
) inputs is entered on the falling edge of the
Clock Pulse (CP) input signal When M is LOW data is shift-
ed out of the most significant bit position while information
present on the Serial (SI) input shifts into the least signifi-
cant bit position A HIGH signal on the Chip Select (CS)
input prevents both parallel and serial operations
Features
Y
Y
Y
Y
16-bit parallel-to-serial conversion
16-bit serial-in serial-out
Chip select control
Slim 24 lead 300 mil package
Commercial
74F676PC
74F676SPC
Military
Package
Number
N24A
N24C
Package Description
24-Lead (0 600 Wide) Molded Dual-In-Line
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead (0 600 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
54F676DM (Note 2)
54F676SDM (Note 2)
74F676SC (Note 1)
54F676FM (Note 2)
54F676LM (Note 2)
Note 1
Devices also available in 13 reel Use suffix
e
SCX
J24A
J24F
M24B
W24C
E28A
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9588 鈥?3
TL F 9588 鈥?2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9588
RRD-B30M105 Printed in U S A