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74F675ASPC Datasheet

  • 74F675ASPC

  • 16-Bit Serial-In, Serial/Parallel-Out Shift Register

  • 66.36KB

  • 6頁

  • FAIRCHILD

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74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
April 1988
Revised August 1999
74F675A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F675A contains a 16-bit serial in/serial out shift reg-
ister and a 16-bit parallel out storage register. Separate
serial input and output pins are provided for expansion to
longer words. By means of a separate clock, the contents
of the shift register are transferred to the storage register.
The contents of the storage register can also be loaded
back into the shift register. A HIGH signal on the Chip
Select input prevents both shifting and parallel loading.
Features
s
Serial-to-parallel converter
s
16-Bit serial I/O shift register
s
16-Bit parallel out storage register
s
Recirculating parallel transfer
s
Expandable for longer words
s
Slim 24 lead package
s
74F675A version prevents false clocking through
CS or R/W inputs
Ordering Code:
Order Number
74F675ASC
74F675APC
74F675ASPC
Package Number
M24B
N24A
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
漏 1999 Fairchild Semiconductor Corporation
DS009587
www.fairchildsemi.com

74F675ASPC 產(chǎn)品屬性

  • 375

  • 集成電路 (IC)

  • 邏輯 - 移位寄存器

  • 74F

  • 移位寄存器

  • 標(biāo)準(zhǔn)

  • 1

  • 16

  • 串行至并行，串行

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 通孔

  • 24-DIP（0.300"，7.62mm）

  • 24-PDIP

  • 管件

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