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74F552 Datasheet

  • 74F552

  • Octal Registered Transceiver with Parity and Flags

  • 8頁

  • FAIRCHILD

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74F552 Octal Registered Transceiver with Parity and Flags
April 1988
Revised March 2000
74F552
Octal Registered Transceiver with Parity and Flags
General Description
The 74F552 octal transceiver contains two 8-bit registers
for temporary storage of data flowing in either direction.
Each register has its own clock pulse and clock enable
input as well as a flag flip-flop that is set automatically as
the register is loaded. The flag output will be reset when
the output enable returns to HIGH after reading the output
port. Each register has a separate output enable control for
its 3-STATE buffer. The separate Clocks, Flags, and
Enables provide considerable flexibility as I/O ports for
demand-response data transfer. When data is transferred
from the A Port to the B Port, a parity bit is generated. On
the other hand, when data is transferred from the B Port to
the A Port, the parity of input data on B
0
鈥揃
7
is checked.
Features
s
8-Bit bidirectional I/O Port with handshake
s
Register status flag flip-flops
s
Separate clock enable and output enable
s
Parity generation and parity check
s
B-outputs sink 64 mA
s
3-STATE outputs
Ordering Code:
Order Number
74F552SC
74F552QC
Package Number
M28B
V28A
Package Description
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
Pin Assignments for SOIC
Pin Assignments for PLCC
漏 2000 Fairchild Semiconductor Corporation
DS009561
www.fairchildsemi.com

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