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74F539PC Datasheet

  • 74F539PC

  • Dual 1-of-4 Decoder with 3-STATE Outputs

  • 6頁(yè)

  • FAIRCHILD

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74F539 Dual 1-of-4 Decoder with 3-STATE Outputs
April 1988
Revised August 1999
74F539
Dual 1-of-4 Decoder with 3-STATE Outputs
General Description
The 74F539 contains two independent decoders. Each
accepts two Address (A
0
, A
1
) input signals and decodes
them to select one of four mutually exclusive outputs. A
polarity control input (P) determines whether the outputs
are active HIGH (P
=
L) or active LOW (P
=
H). An active
LOW input Enable (E) is available for data demultiplexing;
data is routed to the selected output in non-inverted form in
the active LOW mode or in inverted form in the active HIGH
mode. A HIGH signal on the active LOW Output Enable
(OE) input forces the 3-STATE outputs to the high imped-
ance state.
Ordering Code:
Order Number
74F539SC
74F539PC
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
漏 1999 Fairchild Semiconductor Corporation
DS009552
www.fairchildsemi.com

74F539PC 產(chǎn)品屬性

  • Fairchild Semiconductor

  • Decoder / Demultiplexer

  • 74F

  • 1 / 4

  • 5.5 V

  • 4.5 V

  • + 70 C

  • Through Hole

  • DIP-20

  • Rail

  • 0 C

  • 1

  • 4

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