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74F538SC Datasheet

  • 74F538SC

  • 1-of-8 Decoder with 3-STATE Outputs

  • 7頁

  • FAIRCHILD

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74F538 1-of-8 Decoder with 3-STATE Outputs
April 1988
Revised August 1999
74F538
1-of-8 Decoder with 3-STATE Outputs
General Description
The 74F538 decoder/demultiplexer accepts three Address
(A
0
鈥揂
2
) input signals and decodes them to select one of
eight mutually exclusive outputs. A polarity control input (P)
determines whether the outputs are active LOW or active
HIGH. A HIGH Signal on either of the active LOW Output
Enable (OE) inputs forces all outputs to the high imped-
ance state. Two active HIGH and two active LOW input
enables are available for easy expansion to 1-of 32 decod-
ing with four packages, or for data demultiplexing to 1-of-8
or 1-of-16 destinations.
Features
s
Output polarity control
s
Data demultiplexing capability
s
Multiple enables for expansion
s
3-STATE outputs
Ordering Code:
Order Number
74F538SC
74F538SJ
74F538PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
漏 1999 Fairchild Semiconductor Corporation
DS009551
www.fairchildsemi.com

74F538SC 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 編碼器、解碼器、復(fù)用器和解復(fù)用器

  • Decoders, Encoders, Multiplexers & Demultiplexers

  • 74F

  • 1 / 8

  • 5.5 V

  • 4.5 V

  • + 70 C

  • SMD/SMT

  • SOIC-20

  • Rail

  • 0 C

  • 1

  • 8

  • 25920

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