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74F379 Quad Parallel Register with Enable

May 1988

Revised August 1999

74F379

Quad Parallel Register with Enable

General Description

The 74F379 is a 4-bit register with buffered common

Enable. This device is similar to the 74F175 but features

the common Enable rather than common Master Reset.

Features

s

Edge triggered D-type inputs

s

Buffered positive edge-triggered clock

s

Buffered common enable input

s

True and complement outputs

Ordering Code:

Order Number

74F379SC

74F379SJ

74F379PC

Package Number

M16A

M16D

N16E

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

漏 1999 Fairchild Semiconductor Corporation

DS009527

www.fairchildsemi.com

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