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74F273SC Datasheet

  • 74F273SC

  • Octal D-Type Flip-Flop

  • 63.04KB

  • 6頁

  • FAIRCHILD

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74F273 Octal D-Type Flip-Flop
April 1988
Revised August 1999
74F273
Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Ideal buffer for MOS microprocessor or memory
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous Master Reset
s
See 74F377 for clock enable version
s
See 74F373 for transparent latch version
s
See 74F374 for 3-STATE version
Ordering Code:
Order Number
74F273SC
74F273SJ
74F273PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
漏 1999 Fairchild Semiconductor Corporation
DS009511
www.fairchildsemi.com

74F273SC 產(chǎn)品屬性

  • 1,080

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74F

  • 主復(fù)位

  • D 型總線

  • 非反相

  • 1

  • 8

  • 160MHz

  • 7ns

  • 正邊沿

  • 1mA，20mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 管件

  • Q1154995A

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