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74F174SJ Datasheet

  • 74F174SJ

  • Hex D Flip-Flop with Master Reset

  • 8頁(yè)

  • NSC

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54F 74F174 Hex D Flip-Flop with Master Reset
November 1994
54F 74F174 Hex D Flip-Flop with Master Reset
General Description
The 鈥橣174 is a high-speed hex D flip-flop The device is
used primarily as a 6-bit edge-triggered storage register
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition The device has a
Master Reset to simultaneously clear all flip-flops
Features
Y
Y
Y
Y
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
Asynchronous common reset
Guaranteed 4000V minimum ESD protection
Commercial
74F174PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F174DM (Note 2)
74F174SC (Note 1)
74F174SJ (Note 1)
54F174FM (Note 2)
54F174LM (Note 2)
J16A
M16A
M16D
W16A
E20A
Note 1
Devices also available in 13 reel Use Suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9489鈥?
TL F 9489 鈥?1
TL F 9489 鈥?2
IEEE IEC
TL F 9489鈥?
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9489
RRD-B30M75 Printed in U S A

74F174SJ 產(chǎn)品屬性

  • 47

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74F

  • 主復(fù)位

  • D 型總線(xiàn)

  • 非反相

  • 1

  • 6

  • 80MHz

  • 5.5ns

  • 正邊沿

  • 1mA，20mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 16-SOIC（0.209"，5.30mm 寬）

  • 管件

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