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74F113SJ Datasheet

  • 74F113SJ

  • Dual JK Negative Edge-Triggered Flip-Flop

  • 6頁

  • FAIRCHILD

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74F113 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised July 1999
74F113
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip-
flop will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is
transferred to the outputs on the falling edge of the clock
pulse.
Asynchronous input:
LOW input to S
D
sets Q to HIGH level
Set is independent of clock
Ordering Code:
Order Number
74F113SC
74F113SJ
74F113PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
漏 1999 Fairchild Semiconductor Corporation
DS009473
www.fairchildsemi.com

74F113SJ 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 2

  • 74F

  • D-Type Flip-Flop

  • Inverting/Non-Inverting

  • Single-Ended

  • Differential

  • 6 ns

  • - 1 mA

  • 20 mA

  • 5.5 V

  • + 70 C

  • SMD/SMT

  • SOP-14

  • Rail

  • 0 C

  • 2

  • 1

  • 4.5 V

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