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74F112SJ Datasheet

  • 74F112SJ

  • Dual JK Negative Edge-Triggered Flip-Flop

  • 6頁(yè)

  • FAIRCHILD

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74F112 Dual JK Negative Edge-Triggered Flip-Flop
April 1988
Revised July 1999
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on S
D
or C
D
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on S
D
and C
D
force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q
and Q HIGH
Ordering Code:
Order Number
74F112SC
74F112SJ
74F112PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
漏 1999 Fairchild Semiconductor Corporation
DS009472
www.fairchildsemi.com

74F112SJ 產(chǎn)品屬性

  • 47

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74F

  • 設(shè)置（預(yù)設(shè)）和復(fù)位

  • JK 型

  • 差分

  • 2

  • 1

  • 105MHz

  • 5ns

  • 負(fù)邊沿

  • 1mA，20mA

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 16-SOIC（0.209"，5.30mm 寬）

  • 管件

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