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74AVCH2T45DCUTE4 Datasheet

  • 74AVCH2T45DCUTE4

  • DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTA...

  • 23頁

  • TI

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SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES582D 鈥?JULY 2004 鈥?REVISED AUGUST 2005
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
Available in the Texas Instruments
NanoStar鈩?and NanoFree鈩?Packages
Control Inputs V
IH
/V
IL
Levels Are Referenced
to V
CCA
Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
I/Os Are 4.6-V Tolerant
I
off
Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
DCT OR DCU PACKAGE
(TOP VIEW)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Max Data Rates
鈥?500 Mbps (1.8-V to 3.3-V Translation)
鈥?320 Mbps (<1.8-V to 3.3-V Translation)
鈥?320 Mbps (Translate to 2.5 V or 1.8 V)
鈥?180 Mbps (Translate to 1.5 V)
鈥?240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
V
CCA
A1
A2
GND
1
2
3
4
8
7
6
5
V
CCB
B1
B2
DIR
GND
A2
A1
V
CCA
4 5
3 6
2 7
1 8
DIR
B2
B1
V
CCB
DESCRIPTION/ORDERING INFORMATION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVCH2T45 is optimized to operate with V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as
low as 1.2 V. The A port is designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The B
port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH2T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YEP
鈥?0擄C to 85擄C
NanoFree鈩?鈥?WCSP (DSBGA)
0.23-mm Large Bump 鈥?YZP (Pb-free)
SSOP 鈥?DCT
VSSOP 鈥?DCU
(1)
(2)
ORDERABLE PART NUMBER
SN74AVCH2T45YEPR
(3)
Tape and reel
SN74AVCH2T45YZPR
(3)
Tape and reel
Tape and reel
SN74AVCH2T45DCTR
SN74AVCH2T45DCUR
ET2_ _ _
ET2_
TOP-SIDE MARKING
(2)
(3)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
鈥?/div>
= Pb-free).
Package preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2004鈥?005, Texas Instruments Incorporated

74AVCH2T45DCUTE4 產(chǎn)品屬性

  • 250

  • 集成電路 (IC)

  • 邏輯 - 變換器

  • 74AVCH

  • 變換器，雙向，3 態(tài)

  • 2

  • 邏輯

  • 邏輯

  • 500Mbps

  • 2

  • 1

  • 無/無

  • 2.4ns

  • 1.2 V ~ 3.6 V

  • -40°C ~ 85°C

  • 8-VFSOP（0.091"，2.30mm 寬）

  • US8

  • 帶卷 (TR)

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