74ALVCH16374
Low-Voltage 16-Bit D-Type
Flip-Flop with Bus Hold
1.8/2.5/3.3 V
(3鈥揝tate, Non鈥揑nverting)
The 74ALVCH16374 is an advanced performance, non鈥搃nverting
16鈥揵it D鈥搕ype flip鈥揻lop. It is designed for very high鈥搒peed, very
low鈥損ower operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16374 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Clock Pulse inputs. These control pins can be tied together for full
16鈥揵it operation.
The 74ALVCH16374 consists of 16 edge鈥搕riggered flip鈥揻lops with
individual D鈥搕ype inputs and 3.6 V鈥搕olerant 3鈥搒tate outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flip鈥揻lops
within the respective byte. The flip鈥揻lops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOW鈥搕o鈥揌IGH Clock (CP) transition. With the OE LOW, the
contents of the flip鈥揻lops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flip鈥揻lops. The data inputs include
active bushold circuitry, eliminating the need for external pull鈥搖p
resistors to hold unused or floating inputs at a valid logic state.
http://onsemi.com
MARKING DIAGRAM
48
48
74ALVCH16374DT
1
AWLYYWW
TSSOP鈥?8
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN NAMES
Pins
OEn
CPn
D0鈥揇15
O0鈥揙15
Function
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
鈥?/div>
Designed for Low Voltage Operation: VCC = 1.65 鈥?3.6 V
鈥?/div>
3.6 V Tolerant Inputs and Outputs
鈥?/div>
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3.9 ns max for 2.3 to 2.7 V
7.8 ns max for 1.65 to 1.95 V
Static Drive:
鹵24
mA Drive at 3.0 V
鹵18
mA Drive at 2.3 V
鹵6
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
IOFF Specification Guarantees High Impedance When VCC = 0 V
鈥?/div>
Near Zero Static Supply Current in All Three Logic States (20
碌A(chǔ))
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
鹵250
mA @ 125擄C
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
Second Source to Industry Standard 74ALVCH16374
ORDERING INFORMATION
Device
74ALVCH16374DT
74ALVCH16374DTR
Package
TSSOP
TSSOP
Shipping
39 / Rail
2500 / Reel
鈥燭o ensure the outputs activate in the 3鈥搒tate condition, the output enable pins
should be connected to VCC through a pull鈥搖p resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
漏
Semiconductor Components Industries, LLC, 2001
1
November, 2001 鈥?Rev. 1
Publication Order Number:
74ALVCH16374/D
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