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74ALVCH16240DTR Datasheet

  • 74ALVCH16240DTR

  • BUFFER/DRIVER|QUAD|4-BIT|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC

  • 140.17KB

  • 12頁(yè)

  • ETC

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74ALVCH16240
Low-Voltage 16-Bit Buffer
with Bus Hold 1.8/2.5/3.3 V
(3鈥揝tate, Inverting)
The 74ALVCH16240 is an advanced performance, inverting 16鈥揵it
buffer. It is designed for very high鈥搒peed, very low鈥損ower operation
in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16240 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16鈥揵it operation. The 3鈥搒tate outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bus鈥揾old
circuitry, eliminating the need for external pull鈥搖p resistors to hold
unused or floating inputs at a valid logic state.
http://onsemi.com
MARKING DIAGRAM
48
48
1
74ALVCH16240DT
AWLYYWW
鈥?/div>
Designed for Low Voltage Operation: VCC = 1.65 to 3.6 V
鈥?/div>
3.6 V Tolerant Inputs and Outputs
鈥?/div>
High鈥揝peed Operation: 2.5 ns Max for 3.0 to 3.6 V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3.0 ns Max for 2.3 to 2.7 V
6.0 ns Max for 1.65 to 1.95 V
Static Drive:
鹵24
mA Drive at 3.0 V
鹵12
mA Drive at 2.3 V
鹵4
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bus鈥揌old to Hold Unused or Floating Inputs at a
Valid Logic State
IOFF Specification Guarantees High Impedance When VCC = 0 V鈥?/div>
Near Zero Static Supply Current in All Three Logic States (20
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
鹵250
mA @ 85_C
ESD Performance: Human Body Model >2000 V;
Machine Model
u200
V
Second Source to Industry Standard 74ALVCH16240
TSSOP鈥?8
DT SUFFIX
CASE 1201
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
74ALVCH16240DT
74ALVCH16240DTR
Package
TSSOP
TSSOP
Shipping
39 / Rail
2500 / Reel
鈥燭o ensure the outputs activate in the 3鈥搒tate condition, the output enable pins
should be connected to VCC through a pull鈥搖p resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
漏
Semiconductor Components Industries, LLC, 2001
1
November, 2001 鈥?Rev. 1
Publication Order Number:
74ALVCH16240/D

74ALVCH16240DTR 產(chǎn)品屬性

  • 2,500

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74ALVCH

  • 逆變器，緩沖器

  • 4

  • 4

  • 三態(tài)

  • 2.3 V ~ 3.6 V

  • 40µA

  • 24mA，24mA

  • 0.7 V ~ 0.8 V

  • 1.7 V ~ 2 V

  • 3ns @ 3V ~ 3.6V，30pF

  • -40°C ~ 85°C

  • 表面貼裝

  • 48-TSSOP

  • 48-TFSOP（0.240"，6.10mm 寬）

  • 帶卷 (TR)

  • 74ALVCH16240DTROS

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