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74ALVC162839T Datasheet

  • 74ALVC162839T

  • Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tole...

  • 86.72KB

  • 6頁

  • FAIRCHILD

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74ALVC162839 Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26鈩?Series
Resistors in the Outputs
November 2001
Revised November 2001
74ALVC162839
Low Voltage 20-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs/Outputs
and 26
鈩?/div>
Series Resistors in the Outputs
General Description
The ALVC162839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74ALVC162839 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC162839 is also designed with 26
鈩?/div>
series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVC162839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 and PC133 DIMM module
specifications
s
1.65V鈥?.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
鈩?/div>
series resistors in the outputs
s
t
PD
(CLK to O
n
)
4.6 ns max for 3.0V to 3.6V V
CC
6.3 ns max for 2.3V to 2.7V V
CC
9.8 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC162839T
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I
0
鈥揑
19
O
0
鈥揙
19
CLK
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
漏 2001 Fairchild Semiconductor Corporation
DS500712
www.fairchildsemi.com

74ALVC162839T 產(chǎn)品屬性

  • 3,400

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74ALVC

  • 緩沖器/線路驅(qū)動器，非反相

  • 1

  • 20

  • 12mA，12mA

  • 1.65 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 管件

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