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74AHC2G241DC Datasheet

  • 74AHC2G241DC

  • Dual buffer/line driver; 3-state

  • 19頁

  • PHILIPS

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74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
Rev. 01 鈥?10 March 2004
Product data sheet
1. General description
The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device.
The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A
HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW
level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
2. Features
s
Symmetrical output impedance
s
High noise immunity
s
ESD protection:
x
HBM EIA/JESD22-A114-A exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
x
CDM EIA/JESD22-C101 exceeds 1000 V.
s
Low power dissipation
s
Balanced propagation delays
s
SOT505-2 and SOT765-1 package
s
Speci鏗乪d from
鈭?0 擄C
to +85
擄C
and from
鈭?0 擄C
to +125
擄C.
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
擄
C; t
r
= t
f
鈮?/div>
3.0 ns.
Symbol
Parameter
Conditions
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
C
L
= 50 pF; f = 1 MHz
[1] [2]
Min
-
-
-
-
-
-
-
Typ
3.4
3.6
3.6
4.1
4.3
1.5
10
Max
5.5
5.1
5.6
6.8
6.8
10
-
Unit
ns
ns
ns
ns
ns
pF
pF
Type 74AHC2G241
t
PHL
, t
PLH
propagation delay nA to nY
t
PZH
, t
PZL
t
PHZ
, t
PLZ
C
I
C
PD
enable time1OE to 1Y
enable time 2OE to 2Y
disable time1OE to 1Y
disable time 2OE to 2Y
input capacitance
power dissipation
capacitance

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