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74ACTQ74SJ Datasheet

  • 74ACTQ74SJ

  • Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

  • 217.99KB

  • 8頁(yè)

  • FAIRCHILD

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74ACTQ74 Quiet Series Dual D-Type
March 1993
Revised November 1999
74ACTQ74
Quiet Series Dual D-Type
Positive Edge-Triggered Flip-Flop
General Description
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q) out-
puts. Information at the input is transferred to the outputs
on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive-going
pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next
rising edge of the Clock Pulse input.
The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series錚?features
GTO錚?output control and undershoot corrector in addition
to a split ground bus for superior performance.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes
both Q and Q HIGH
Features
s
I
CC
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
4 kV minimum ESD immunity
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACTQ74SC
74ACTQ74SJ
74ACTQ74PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering form.
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT錚? FACT Quiet Series錚?and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS010920
www.fairchildsemi.com

74ACTQ74SJ 產(chǎn)品屬性

  • 47

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74ACTQ

  • 設(shè)置（預(yù)設(shè)）和復(fù)位

  • D 型

  • 差分

  • 2

  • 1

  • 200MHz

  • 7ns

  • 正邊沿

  • 24mA，24mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 14-SOIC（0.209"，5.30mm 寬）

  • 管件

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