74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs
January 1990
Revised November 1999
74ACTQ533
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data satisfying the input tim-
ing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
The ACTQ533 utilizes Fairchild Quiet Series錚?technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO錚?/div>
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch up immunity
s
Eight latches in a single package
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Inverted version of the ACTQ373
s
4 kV minimum ESD immunity
Ordering Code:
Order Number
74ACTQ533SC
74ACTQ533MTC
74ACTQ533PC
Package Number
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide Body
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
FACT錚? FACT Quiet Series錚? and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
漏 1999 Fairchild Semiconductor Corporation
DS010630
www.fairchildsemi.com
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