錚?/div>
output control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
Inverting 3-STATE outputs drive bus lines or buffer
memory address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard ACT240
Ordering Code:
Order Number
74ACQ240SC
74ACQ240SJ
74ACQ240PC
74ACTQ240SC
74ACTQ240SJ
74ACTQ240QSC
74ACTQ240PC
Package Number
M20B
M20D
N20A
M20B
M20D
MQA20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
FACT錚? Quiet Series錚? FACT Quiet Series錚? and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
漏 2000 Fairchild Semiconductor Corporation
DS010234
www.fairchildsemi.com