74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
September 1991
Revised November 1999
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
The ACTQ18823 utilizes Fairchild鈥檚 Quiet Series錚?technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series錚?fea-
tures GTO錚?output control and undershoot corrector for
superior performance.
Features
s
Utilizes Fairchild鈥檚 FACT Quiet Series technology
s
Broadside pinout allows for easy board layout
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ18823SSC
74ACTQ18823MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
CLR
n
EN
n
CP
n
I
0
鈥揑
17
O
0
鈥揙
17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT錚? Quiet Series錚? FACT Quiet Series錚? and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS010953
www.fairchildsemi.com