74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
May 1991
Revised November 1998
74ACTQ16240
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16240 utilizes Fairchild鈥檚 Quiet Series鈩?technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series鈩?fea-
tures GTO鈩?output control for superior performance.
Features
s
Utilizes Fairchild鈥檚 FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
16-bit version of the ACTQ240
s
Outputs source/sink 24 mA
s
Additional specs for multiple output switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ16240SSC
74ACTQ16240MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment
for SSOP and TSSOP
Pin Descriptions
Pin Names
OE
n
I
0
鈥揑
15
O
0
鈥揙
15
Description
Output Enable Inputs (Active Low)
Inputs
Outputs
FACT鈩? FACT Quiet Series鈩? Quiet Series鈩? and GTO鈩?are trademarks of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS010924.prf
www.fairchildsemi.com
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