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74ACT74PC Datasheet

  • 74ACT74PC

  • Dual D-Type Positive Edge-Triggered Flip-Flop

  • 9頁

  • FAIRCHILD

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74AC74 鈥?74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
November 1988
Revised November 1999
74AC74 鈥?74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
s
I
CC
reduced by 50%
s
Output source/sink 24 mA
s
ACT74 has TTL-compatible inputs
Ordering Code:
Order Number
74AC74SC
74AC74SJ
74AC74MTC
74AC74PC
74ACT74SC
74ACT74SJ
74ACT74MTC
74ACT74PC
Package Number
M14A
M14D
MTC14
N14A
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT錚?is a trademark of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS009920
www.fairchildsemi.com

74ACT74PC 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74ACT

  • 設(shè)置（預(yù)設(shè)）和復(fù)位

  • D 型

  • 差分

  • 2

  • 1

  • 210MHz

  • 7.5ns

  • 正邊沿

  • 24mA，24mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 通孔

  • 14-DIP（0.300"，7.62mm）

  • 管件

  • 74ACT74

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