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74ACT74M Datasheet

  • 74ACT74M

  • DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

  • 11頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 250 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT74B
74ACT74M
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The ACT74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and
double-layer metal
wiring
C
2
MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/11

74ACT74M 產(chǎn)品屬性

  • STMicroelectronics

  • 觸發(fā)器

  • 2

  • 74ACT

  • D-Type Flip-Flop

  • Inverting/Non-Inverting

  • Single-Ended

  • Differential

  • 10 ns

  • - 24 mA

  • 24 mA

  • 5.5 V

  • + 125 C

  • SMD/SMT

  • SOP-14

  • Tube

  • - 55 C

  • 1

  • 1

  • 50

  • 4.5 V

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