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74ACT573M Datasheet

  • 74ACT573M

  • OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

  • 11頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74ACT573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4碌A(chǔ)(MAX.) at T
A
=25擄C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT573B
74ACT573M
T&R
74ACT573MTR
74ACT573TTR
DESCRIPTION
The 74ACT573 is an advanced high-speed CMOS
OCTAL D-TYPE LATCH with 3 STATE OUTPUT
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input .
PIN CONNECTION AND IEC LOGIC SYMBOLS
When the LE is taken low, the Q outputs will be
latched precisely or inversely at the logic level of D
input data. While the (OE) input is low, the 8
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
1/11

74ACT573M 產(chǎn)品屬性

  • STMicroelectronics

  • 閉鎖

  • 8

  • D-Type Latch

  • 74AC

  • Non-Inverting

  • 3

  • - 24 mA

  • 32 mA

  • 10 ns at 5 V

  • 5.5 V

  • 4.5 V

  • + 125 C

  • - 55 C

  • SOP-20

  • Tube

  • SMD/SMT

  • 8

  • 40

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