74ACT533 Octal Transparent Latch with 3-STATE Outputs
August 1999
Revised October 1999
74ACT533
Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACT533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Eight latches in a single package
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Inverted version of the ACT373
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT533SC
74ACT533MTC
74ACT533PC
Package Number
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide Body
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
FACT鈩?is a trademark of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS500311
www.fairchildsemi.com