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74ACT18825MTD Datasheet

  • 74ACT18825MTD

  • 18-Bit Buffer/Line Driver with 3-STATE Outputs

  • 6頁

  • FAIRCHILD

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74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs
August 1999
Revised October 1999
74ACT18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
Features
s
Broadside pinout allows for easy board layout
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT18825SSC
74ACT18825MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
I
0
鈥揑
17
O
0
鈥揙
17
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT鈩? FACT Quiet Series鈩?and GTO鈩?are trademarks of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS0500292
www.fairchildsemi.com

74ACT18825MTD 產(chǎn)品屬性

  • 34

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器

  • 74ACT

  • 緩沖器/線路驅(qū)動器，非反相

  • 2

  • 9

  • 24mA，24mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 管件

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