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74ACT16543DLRG4 Datasheet

  • 74ACT16543DLRG4

  • 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

  • 10頁(yè)

  • TI

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54ACT16543, 74ACT16543
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS126B 鈥?MARCH 1990 鈥?REVISED APRIL 1996
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
鈩?/div>
Family
Inputs Are TTL-Voltage Compatible
3-State True Outputs
Flow-Through Architecture Optimizes
PCB Layout
Distributed V
CC
and GND Pin
Configurations Minimize High-Speed
Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings, and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
54ACT16543 . . . WD PACKAGE
74ACT16543 . . . DGG OR DL PACKAGE
(TOP VIEW)
description
The 鈥橝CT16543 are 16-bit registered transceivers
that contain two sets of D-type latches for
temporary storage of data flowing in either
direction. The 鈥橝CT16543 can be used as two
8-bit transceivers or one 16-bit transceiver.
Separate latch enable (LEAB or LEBA) and
output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
The A-to-B enable (CEAB) and OEAB inputs must
be low to enter data from A or to output data to B.
Having CEAB low and LEAB low makes the
A-to-B latches transparent; a subsequent low-to-
high transition at LEAB puts the A latches in the
storage mode. Data flow from B to A is similar, but
requires using the CEBA, LEBA, and OEBA
inputs.
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The 74ACT16543 is packaged in TI鈥檚 shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54ACT16543 is characterized for operation over the full military temperature range of 鈥?5擄C to 125擄C. The
74ACT16543 is characterized for operation from 鈥?0擄C to 85擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1996, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1

74ACT16543DLRG4 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74ACT

  • 寄存收發(fā)器，非反相

  • 2

  • 8

  • 24mA，24mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-BSSOP（0.295"，7.50mm 寬）

  • 56-SSOP

  • 帶卷 (TR)

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