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Inputs Are TTL-Voltage Compatible
Contains Eight D-Type Flip-Flops
Clock Enable Latched to Avoid False
Clocking
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125擄C
Package Options Include Plastic
Small-Outline Packages, Plastic Shrink
Small-Outline Packages and Standard
Plastic 300-mil DIPs
DB, DW OR NT PACKAGE
(TOP VIEW)
t
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKEN
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLK
description
These circuits are positive-edge-triggered D-type flip-flops with a clock enable input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and
is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high
or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking
by transitions at the CLKEN input.
The 74ACT11377 is characterized for operation from 鈥?40擄C to 85擄C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLKEN
H
L
L
X
CLK
X
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L
D
X
H
L
X
OUTPUT
Q
Q0
H
L
Q0
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
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