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74ACT10M Datasheet

  • 74ACT10M

  • TRIPLE 3-INPUT NAND GATE

  • 7頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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74ACT10
TRIPLE 3-INPUT NAND GATE
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 6.5 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 10
IMPROVED LATCH-UP IMMUNITY
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT10B
74ACT10M
operation similar to equivalent Bipolar Schottky
TTL.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The ACT10 is an advanced high-speed CMOS
TRIPLE 3-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
power applications mantaining high speed
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
1/7

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